Working as an embedded systems consultant, I have to quickly switch between projects or sometimes between different boards for the same project or client. When I was looking for inspiration on how to set up my workbench, I found this blog post from Jay Carlson about the project tray system. https://jaycarlson.net/2021/09/18/juggle-embedded-projects-home-office-workspace-tour/ Jay uses lunch trays […]
Project Tray System Read More »
Welcome to the first blog post of the AMD FPGA video series. When I was at my parents’ house a couple of months ago, I dug out my very first FPGA board. A digilent board with a Spartan 3 FPGA. It was the first time you could get a decent size FPGA board for a
AMD FPGA series – #1 Running ISE on Widows, Linux, and Docker Read More »
Welcome to the blog post number 3 in the Microchip PolarFire SoC series! Today, we’re integrating a custom IP into the PolarFire SoC video kit’s base design, addressing a key aspect of practical FPGA development. We’re going to add the system version IP that I have created for the FPGA meets devops video series, but
Microchip Polarfire SoC series – Custom IP Read More »
Welcome to the blog post number 2 in the Microchip PolarFire SoC series! Today, we’re creating a basic design for the PolarFire SoC video kit from scratch. While in the previous blog post we’ve seen how to build the reference design, it is important to be able to create a design from scratch. Until you
Microchip Polarfire SoC series – Basic design Read More »
Welcome to the first blog post in the Microchip PolarFire SoC series! I am going to show you how to set up the tools, build the reference design, and program the board. More blog posts are coming, diving deeper into the tools, device features, and much more! Video If you prefer this content in video
In the previous blog post we integrated Vivado with GitLab CI to automatically build the FPGA bitstream. What about simulation? In this video I am going to show you how to run and debug cocotb test cases locally and then how to run them with Gitlab CI. Video If you prefer this content in video
FPGA meets DevOps – Simulation with Cocotb Read More »
In the previous blog post we created a system that automatically builds the FPGA bitstream and Linux image. Let’s imagine a bug has been found after a bitstream or Linux image has been released. The questions we need to answer to fix the problem are: What is the version with the bug? What is the
FPGA meets DevOps – System, FPGA, and PetaLinux versioning Read More »
In the previous blog post [link] I have shown you how to use version control (git in particular) for Xilinx/AMD Vivado and Petalinux projects. In this blog post, we’re going to integrate AMD/Xilinx Vivado and Petalinux with Gitlab CI. Video If you prefer this content in video format, it is embedded below. https://youtu.be/bZfZgc4Phtc GitLab Runners
FPGA meets DevOps – AMD/Xilinx Vivado and Petalinux integration with Docker and GitLab Read More »
Video If you prefer this content in video format, the link is below. https://youtu.be/3Og3h0VNiUg Requirements In this blog post of the series “FPGA meets DevOps”, I am going to show you how to use source version control with AMD/Xilinx Vivado. Most of the existing documentation about source version control and Vivado, i.e. User Guide 1198
FPGA meets DevOps – AMD / Xilinx Vivado, Petalinux, and Git Read More »
Why DevOps for FPGA development? During the development and support phase of a product containing an FPGA bitstreams are released containing new features, bug fixes etc. Releases are more frequent during the development phase as new features are added to the design. The support phase can last from a couple of years for a consumer
FPGA meets DevOps – Introduction Read More »
