This email address is being protected from spambots. You need JavaScript enabled to view it.

  • Home
  • Blog
  • FPGA meets DevOps - System and FPGA version

FPGA meets DevOps - System and FPGA version

In the previous blog posts we have created a system to build automatically (or with a single button) the FPGA bitstream.

Let’s imagine a bug is flagged after a bitstream has been released. The questions we need to answer to fix the problem are:

  1. What is the version affected?
  2. What is the source code set that was used to build that particular version?

Now that we have Jenkins building the FPGA bitstream, we can store version and build number inside the FPGA as register readable from a microprocessor. The version has format major.minor.buildnumber. Major and minor are assigned by the designer while the buildnumber is the Jenkins build number. When the Jenkins job is running, the build number is exported as the environment variable BUILD_NUMBER.

I have created a simple system version IP core block for Xilinx Vivado where major and minor version numbers can be configured from the block design GUI and the build number is the Jenkins build number.

blog04 vivado blockdia

blog04 block version

The build_bitstream.tcl script has been updated to set the build number in the system version IP core.

set project_name [get_property NAME [current_project]]
open_bd_design "bd/${project_name}/${project_name}.bd"
set systemversion_block [get_bd_cells *systemversion*]
if {$systemversion_block ne ""} then {
if {[info exists ::env(BUILD_NUMBER)]} {
set build_number $::env(BUILD_NUMBER)
} else {
set build_number 65535
}
puts "Build number ${build_number}"
set_property CONFIG.C_VER_BUILD $build_number $systemversion_block
validate_bd_design
save_bd_design
}
close_bd_design [current_bd_design]

The complete source code is available on github (IP repo and example project).

Now to answer question 1) add the system version IP core to your design and provision a way to read the version from the system i.e. print it on the console when the system starts. Once the infrastructure is in the place, the build number will be stored inside the FPGA bitstream automatically.

Given the build number it is straightforward to get the source code used to build that particular bitstream. Select the build in Jenkins and next to Revision there is the commit hash used to build the bitstream.

blog04 jenkins

The system version IP core has also inputs for board type and revision. For example the same the bitstream can be used on different boards, but the software might be expose different features based on the board type. Similarly the software might need to run on different board revisions. Configure the board_type and board_rev pins with internal pull-down and tie them to VCCIO to set a particular board type/version.

 

If you missed the previous blog posts, you can find them here. Follow Starware Design on Twitter @starwaredesign to get notified of new blog posts.

 

Tags: devops, Zynq, Xilinx, fpga

About us

Starware Design provides design and consulting services for FPGA, board-level and embedded software projects.


Whether you need a consultant to be part of your team on-site or a turnkey solution, Starware Design has the capability to suit your requirements.