In this blog post of the series “FPGA meets DevOps”, I am going to show you how to use source version control with Xilinx Vivado.
Most of the existing documentation about source version control and Vivado, i.e. User Guide 1198 (https://www.xilinx.com/support/documentation/sw_manuals/xilinx2016_3/ug1198-vivado-revision-control-tutorial.pdf), requires the developer to write a TCL script to recreate the project.
The problem with this approach is that changes to the project in Vivado (i.e. changing the implementation strategy or place and route parameters) have to be manually ported to the TCL file.
My typical Xilinx Vivado FPGA project has a block design as top level with automatically generated and managed wrapper. It has a mix of Xilinx and custom IP cores and I use the Out Of Context flow for synthesis since it reduces build time by caching IP cores that haven’t been modified or updated.
When I started researching how to better integrate Vivado with source version control, I defined the following requirements:
- The block design is the primary source to recreate the design (IP cores configuration, wiring, etc)
- The top level wrapper HDL file shouldn’t be under version control since it can be recreated from the block diagram
- Minimum TCL scripts coding for each project
- Easy to save changes made in Vivado GUI (i.e. implementation settings)
- Use the project-based out of context flow to reduces build time
- Continuous Integration friendly
Why DevOps for FPGA development?
During the development and support phase of a product containing an FPGA bitstreams are released containing new features, bug fixes etc.
Releases are more frequent during the development phase as new features are added to the design. The support phase can last from a couple of years for a consumer product to five or more years for an industrial product.