Microchip Polarfire SoC series - #2 Basic design

Welcome to the blog post number 2 in the Microchip PolarFire SoC series! Today, we’re creating a basic design for the PolarFire SoC video kit from scratch. While in the previous blog post we’ve seen how to build the reference design, it is important to be able to create a design from scratch. Until you do, you might miss some important details.

We’re going to create a custom MSS configuration and an FPGA design with two GPIO banks connected to the LEDs and dip switches on the video kit.

We’re going to add support for the GPIO banks to the Linux kernel, and write some examples in Python for testing.

I assume you’ve read the first blog post of the Microchip Polarfire SoC series since I did explain about how to install the tools, build the HSS firmware, Yocto image, etc.

Full disclaimer: this video is not sponsored by Microchip and the video kit has been bought by Starware Design.

FPGA meets DevOps - System, FPGA, and PetaLinux versioning

In the previous blog post we created a system that automatically builds the FPGA bitstream and Linux image.
Let’s imagine a bug has been found after a bitstream or Linux image has been released. The questions we need to answer to fix the problem are:

What is the version with the bug?
What is the source code that was used to build that particular version?

By the end of this blog post we will be able to answer those questions for FPGA bitstream and Linux image, but also to identify a particular board i.e. for RMA.

Microchip Polarfire SoC series - #1 Installing the tools and building the video kit reference design

Welcome to the first blog post in the Microchip PolarFire SoC series! I am going to show you how to set up the tools, build the reference design, and program the board.

More blog posts are coming, diving deeper into the tools, device features, and much more!

Full disclaimer: this video is not sponsored by Microchip and the video kit has been bought by Starware Design.

FPGA meets DevOps UPDATED! - AMD / Xilinx Vivado and Petalinux + Git

A couple of years ago I wrote a few blog posts regarding FPGA and devops; in particular on how to use Xilinx/AMD Vivado with git, Jenkins and docker.

With these new blog posts, I am going to update that content using Vivado 2022.2. I will also replace Jenkins with Gitlab for continuous integration.

I want to show you that it is not difficult nor expensive to get started with devops for FPGA development.

In this blog post, I am going to show you how to use version control for Xilinx/AMD Vivado and Petalinux projects. I am going to use git, but you can use SVN or other version control tools.

FPGA meets DevOps UPDATED! - AMD/Xilinx Vivado and Petalinux integration with Docker and GitLab

In the previous blog post [link] I have shown you how to use version control (git in particular) for Xilinx/AMD Vivado and Petalinux projects.

In this blog post, we’re going to integrate AMD/Xilinx Vivado and Petalinux with Gitlab CI.

Microchip Polarfire SoC series - #2 Basic design

FPGA meets DevOps - System, FPGA, and PetaLinux versioning

Microchip Polarfire SoC series - #1 Installing the tools and building the video kit reference design

FPGA meets DevOps UPDATED! - AMD / Xilinx Vivado and Petalinux + Git

FPGA meets DevOps UPDATED! - AMD/Xilinx Vivado and Petalinux integration with Docker and GitLab

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